Die-to-wafer technique is an attractive technique, in which the die from one wafer are diced and then joined to another die or to a wafer. Thus, only good die are joined together, dissimilar technologies can be joined, and alignment tolerances are less stringent. Die mixing can be done so that the fastest memory die can be matched to the faster logic die. Die to wafer can be used for wafer reconstruction to enable wafer stacking with dice featuring different sizes.

 Chip stacking or chip-to-wafer approach also called 3D-ICs suffers from low throughput potential since each die is placed individually prior to being bonding individually or globally after placement of all dice. However, this inconvenient is balanced by the benefit of bonding known good die to known good bonding site to the wafer, increasing yield significantly. Another tremendous advantage is the capability of mixing dissimilar technologies either side by side or as a stack: the fastest memory die can be matched to the faster logic die. Chip-to-wafer bonding is also used for wafer rebuilding or chip resizing and connection redistribution in order to achieve 3D die-stack of different technologies.