For a couple of years, SET is discussing thoroughly with the various component assembly actors the “More-than-Moore” 3D integration concept which is expected to maintain Moore’s Law . The development of 3D IC solutions is driven by form factor, performances, power consumption, heterogeneous integration and cost. Within the various technologies envisioned for the 3D-IC integration, the high density Through Silicon Via (TSV) technology is of the highest interest to SET who is specializing for over three decades in high accuracy high flexibility die and flip chip bonders.		FC300 Confinement Chamber

One of the advantages of 3D integration is the possibility to integrate components of different technologies. The assembly of infrared focal plane arrays, which are being successfully assembled on SET machine since the early 80’s, is the state of the art example of heterogeneous integration using the flip chip die-to-die bonding approach with millions of bumps as small as 6 µm diameter and 15 µm pitch.

		Die-to-Die or Die-to-Wafer bonding is complementary to the Wafer-to-Wafer bonding technique. Wafer stacking has the advantage of higher throughput as many dies are being bonded simultaneously, but it suffers of significant yield loss with the increasing number of layers and cannot combine chips of different sizes. Die stacking or Die-to-Wafer approach enables the assembly of known good die and combination of dies featuring different sizes or aspect ratios. The main drawback is the lower throughput due to the individual die placement. The development of next generation high throughput, high accuracy bonding equipment is still to come.

In 2007, SET has introduced the FC300, a High Force, High Accuracy Die and Flip Chip Bonder for Die-to-Die and Die-to-Wafer bonding for 300mm wafers. The FC300, which features high process flexibility, is an intermediate step aiming to refine the process prior to defining the requirement of the next generation production tool. It is very likely that next generation tools will integrate several steps to enable high speed bonding; a secured placement of all the dices on the wafer being followed by a global bonding either by thermo-compression or global reflow.

To support its effort in developing the appropriate tool required for the 3D-IC integration, SET will enter the 3D-Integration program of IMEC through a Joint Development Program (JDP) which includes the delivery of a FC300 in 2009.

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